The present invention relates to a multilayer wiring substrate and, more particularly, to a multilayer wiring substrate having a plurality of power supply wiring layers.
An example of conventional ceramic multilayer wiring substrates is disclosed in U.S. Pat. No. 4,245,273. The prior art substrate of that patent has a plurality of integrated circuit (IC) chips on the top surface thereof, a plurality of input/output (I/O) pins used as I/O terminals, a plurality of power pins used as power supply terminals on the bottom surface of said substrate, and a plurality of power supply wiring layers provided therein to supply predetermined different voltages to the IC chips and other electrical components provided on the substrate. However, as described later in detail by referring to the drawings, the laminated structure of the power supply wiring layers in the prior art substrate has a disadvantage in that it is not easy to obtain a predetermined voltage from a desired power supply wiring layer at a desired location on the substrate. Another disadvantage of the prior art substrate is that when the signal wiring layers and the insulating layers, formed by a thick film technique using an inorganic insulating paste, are alternately formed on the substrate, the resistance values of via-hole wirings for the power supply, which penetrate the, insulating layers, are undesirably larger because of the large thickness of each of the insulating layers.
An object of the present invention is, therefore, to provide a substrate free from the above-mentioned disadvantages of the prior art substrate.